`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:06:27 06/15/2015
// Design Name:   ALU
// Module Name:   D:/Libraries/Documents/Ingenieria en Comp/MIPS/trunk/Final-Mips/TestALU.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ALU
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestALU;

	// Inputs
	reg [3:0] A;
	reg [3:0] B;
	reg [5:0] COD_OP;
	reg [4:0] SA;
	

	// Outputs
	wire [3:0] C;
	wire Zero;

	// Instantiate the Unit Under Test (UUT)
	ALU #(4) uut (
		.A(A), 
		.B(B), 
		.COD_OP(COD_OP), 
		.C(C),
		.SA(SA),
		.Zero(Zero)
	);

	initial begin
		// Initialize Inputs
		A = 0;
		B = 0;
		COD_OP = 0;
		SA = 0;
		// Wait 100 ns for global reset to finish
		#100;  
		// Add stimulus here
		
		/***** SUMA SIGNED ******/
		A = 4'b 1; // 1
		B =  -(4'b 0011); // -3
		COD_OP = 6'b 100000;
		//Overflow - moco
		#100;
		A = 4'b 0111; // 7
		B =  4'b 0010; // 2
		
		/***** RESTA SIGNED ******/
		#100;
		COD_OP = 6'b 100010;
		A = 4'b 0010; // 2 - (-5)
		B = -(4'b 0101);
		
		//ZERO 
		#100;
		A = 4'b 0111; // 7
		B =  4'b 0111; // 2
		
		/***** SUMA UNSIGNED ******/
		#100;
		COD_OP = 6'b 100001;
		A = 4'b 0111; // 7
		B =  4'b 1000; // 8
		
		/***** RESTA UNSIGNED ******/
		#100;
		COD_OP = 6'b 100010;
		A = 4'b 0111; // 7
		B =  4'b 0100; // 4
		#100;
		A = 4'b 0111; // 7
		B =  4'b 1001; // 9
		
		/***** SET ON LESS THAN ******/
		#100;
		COD_OP = 6'b 101010;
		A = 4'b 0011; // 3
		B =  4'b 0100; // 4 //Salida == 1
		#100;
		A = 4'b 0111; // 7
		B =  -(4'b 0010); // -2 //Salida = 0
		
		/***** SET UNSIGNED ******/
		#100;
		COD_OP = 6'b 101011;
		A = 4'b 0111; // 7
		B =  4'b 0100; // 4 //Salida == 0
		#100;
		A = 4'b 0111; // 7
		B =  4'b 1000; // 8 //Salida = 1 
		
		/***** SHIFT RIGHT A ******/
		#100;
		COD_OP = 6'b 000011;
		B = 4'b 0100; // 4
		SA = 1;
		#100;
		B = 4'b 1000; // -8
		
		/***** SHIFT RIGHT A V ******/
		#100;
		COD_OP = 6'b 000111;
		B = 4'b 0100; // 4
		A = 2;
		#100;
		B = 4'b 1000; // -8
		
		/***** SHIFT LEFT L ******/
		#100;
		COD_OP = 6'b 000000;
		B = 4'b 0010; // 2
		SA = 2;
		#100;
	
		
		/***** SHIFT LEFT L V ******/
		#100;
		COD_OP = 6'b 000100;
		B = 4'b 0001; // 1
		A = 2;
		#100;
		
	end
      
endmodule

